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DATA BULLETIN
CMX589A
Features
Data Rates from 4kbps to 200kbps Full or Half Duplex Gaussian Filter & Data Recovery for Minimum Shift Keying (GMSK) Designs Selectable BT: (0.3 or 0.5) Low Power 3.0V, 20kbps, 1.5mA typ. 5.0V, 64kbps, 4.0mA typ. Low Current Non-DSP Solution Small TSSOP size fits PCMCIA / PC CARDs
TX ENABLE TX PS TX DATA XTAL/CLOCK XTAL ClkDIVA ClkDIVB BT VDD RXHold PLLacq RXDCacq
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HIGH-SPEED GMSK MODEM
PRELIMINARY INFORMATION
Applications
Portable Wireless Data Applications Cellular Digital Packet Data (CDPD) Mobitex Mobile Data System Spread Spectrum Data Links GPS/Differential GPS Wireless Links Point of Sale Terminals Low Power Wireless Data Link for PCs, Laptops, and Printers

VBIAS DATA RETIME & LEVEL SHIFT TX FILTER
VBIAS TX OUT TX CLK
CLOCK DIVIDER
RX DATA DETECTION RX S/N DETECTION
RX DATA
RX S/N
RX CIRCUIT CONTROL VBIAS + RX FILTER
RX CLOCK
RX CLK VSS
RX PS RX SIGNAL IN RX FEEDBACK
RX DC LEVEL MEASURE DOC1 DOC2
VBIAS
The CMX589A is a single-chip synchronous data pump/modem designed for Wireless Data Applications. Employing Gaussian filtering for Minimum shift Keying (GMSK) baseband modulation applications, the CMX589A features a wide range of available data rates from 4k to 200kbps. Data Rates and the choice of BT (0.3 or 0.5) are pin programmable to provide for different system requirements. The Tx and Rx digital data interfaces are bit serial, synchronized to generated Tx and Rx data clocks. Separate Tx and Rx Powersave inputs allow full or half-duplex operation. Rx input levels can be set by suitable AC and DC level adjusting circuitry built with external components around an on-chip Rx Input Amplifier. Acquisition, Lock, and Hold of Rx data signals are made easier and faster by the use of Rx Control Inputs to clamp, detect, and /or hold input data levels and can be set by the Processor as required. The Rx S/N output provides an indication of the quality of the received signal. The CMX589A may be used with a 3.0V to 5.5V power supply and is available in the following packages: 24-pin TSSOP (CMX589AE2), 24-pin SSOP (CMX589AD5), 24-pin SOIC (CMX589AD2), and 24-pin PDIP (CMX589AP4).
1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
2
CMX589A PRELIMINARY INFORMATION
Contents
Section Page 1 Block Diagram................................................................................................................ 3 2 Signal List....................................................................................................................... 4 3 External Components.................................................................................................... 6 4 General Description....................................................................................................... 8
4.1 4.2 Clock Oscillator Divider ....................................................................................................... 8 Receive................................................................................................................................ 8
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Rx Signal Path Description..................................................................................................... 8 Rx Circuit Control Modes ....................................................................................................... 9 Rx Clock Extraction .............................................................................................................. 10 Rx Data Extraction ............................................................................................................... 10 Rx S/N Detection.................................................................................................................. 11 Rx Signal Quality.................................................................................................................. 12 TX Signal Path Description .................................................................................................. 12
4.3 4.4 4.5
Transmit............................................................................................................................. 12
4.3.1
Data Formats..................................................................................................................... 14 Acquisition and Hold Modes .............................................................................................. 14
5 Application ................................................................................................................... 15
5.1 Radio Channel Requirements ........................................................................................... 15
5.1.1 5.1.2 5.1.3 Bit Rate, BT, and Bandwidth ................................................................................................ 15 FM Modulator, Demodulator and IF ..................................................................................... 15 Two-Point Modulation........................................................................................................... 16
5.2
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AC Coupling of Tx and Rx Signals .................................................................................... 17
6 Performance Specifications........................................................................................ 18
6.1 Electrical Specifications..................................................................................................... 18
6.1.1 6.1.2 6.1.3 Absolute Maximum Limits .................................................................................................... 18 Operating Limits ................................................................................................................... 18 Operating Characteristics..................................................................................................... 19
6.2
Packages........................................................................................................................... 20
MXCOM, Inc. reserves the right to change specifications at any time without notice.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
3
CMX589A PRELIMINARY INFORMATION
1 Block Diagram
TX ENABLE TX PS TX DATA XTAL/CLOCK XTAL ClkDIVA ClkDIVB BT VDD RXHold PLLacq RXDCacq VBIAS + RX FILTER RX DC LEVEL MEASURE DOC1
Figure 1: Block Diagram
VBIAS DATA RETIME & LEVEL SHIFT TX FILTER
VBIAS TX OUT TX CLK
CLOCK DIVIDER
RX DATA DETECTION RX S/N DETECTION
RX DATA
RX S/N
RX CIRCUIT CONTROL
RX CLOCK
RX CLK VSS VBIAS
RX PS RX SIGNAL IN RX FEEDBACK
DOC2
RX Frequency Discriminator
Frequency Modulator
DC Level Adjust RX Sig In
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RX Filter and Gain Signal and DC Level Adjustment
RX Feedback
RX circuits
TX circuits
TX Out
uController or UART
RXD RXC TXD TXC
RX Data RX Clock TX Data TX Clock
CMX589A GMSK MODEM
TX Out Filter
Figure 2: System Block Diagram
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
4
CMX589A PRELIMINARY INFORMATION
2 Signal List
Pin No. E2/D5/ D2/P4 1 2 Signal Type Description
XTAL XTAL/CLOCK
output input
The output of the on-chip clock oscillator. The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock (fXTAL) pulse input should be connected here. If an externally generated clock is to be used, it should be connected to this pin and the XTAL pin left unconnected. Note: Operation without a suitable Xtal or clock input may cause device damage. Logic level inputs control the internal clock divider and therefore the transmit and receive data rate. See Table 4. Logic level inputs control the internal clock divider and therefore the transmit and receive data rate. See Table 4. A logic 0 applied to this input will freeze the Clock Extraction and Level Measurement circuits unless they are in `Acquire' mode. A logic 1 applied to this input will set the RX Level Measurement circuitry to the Acquire mode. A logic 1 applied to this input will set the RX Clock Extraction circuitry to the `Acquire' mode. See Table 6. A logic 1 applied to this input will powersave all receive circuits except for RX CLK output (which will continue at the set bit-rate) and cause the RX Data and RX S/N outputs to go to a logic 0. The internal circuitry bias line, held at VDD/2. This pin must be bypassed to VSS by a capacitor mounted close to the pin. Output of the RX Input Amplifier. Input to RX input amplifier. Negative supply (GND). Connections to the RX Level Measurement Circuitry. A capacitor should be connected from each pin to VSS. Connections to the RX Level Measurement Circuitry. A capacitor should be connected from each pin to VSS. A logic level to select the modem BT (the ratio of the TX Filter's -3dB frequency to the Bit-Rate). A logic 1 = BT of 0.5 and a logic 0 = BT of 0.3. Gaussian filtered TX output signal. In powersave mode the Tx Out pin is a high impedance open. A logic 1 applied to this input, enables the transmit data path, through the TX Filter to the TX Out pin. A logic 0 will place the TX Out pin to VBIAS via a high impedance. A logic 1 applied to this input will powersave all transmit circuits except for the TX Clock. The logic level input for the data to be transmitted. This data should be synchronous with TX CLK. A logic level output carrying the received data, synchronous with RX CLK. A logic level clock output at the received data bit-rate. A logic level clock output at the transmit-data rate.
3 4 5 6 7 8
ClkDivA ClkDivB
input input input input input input
Rx HOLD
RxDCacq PLLacq Rx PSAVE
9 10 11 12 13 14
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VBIAS Rx FB Rx Signal In VSS DOC1 DOC2 BT
input power
15
16 17
Tx Out Tx Enable
output input
18 19 20 21 22
Tx PSAVE Tx Data Rx Data Rx CLK Tx CLK
input input output output output
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
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5
CMX589A PRELIMINARY INFORMATION
Pin No. E2/D5/ D2/P4 23 24
Signal
Type
Description
Rx S/N VDD
output power
A logic level output which may be used as an indication of the quality of the received signal. Positive supply. Levels and voltages within the device are dependent upon this supply. This pin should be bypassed to VSS by a capacitor mounted close to the pin. Table 1: Signal List
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1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
6
CMX589A PRELIMINARY INFORMATION
3 External Components
XTAL XTAL/CLOCK ClkDivA ClkDivB RX HOLD RXDCacq PLLacq
C5 R4 R3 C6
RX PSAVE VBIAS RX FB RX SIGNAL IN VSS
1 2 3 4 5 6 7 8 9 10 11 12
CMX589A E2/D5/D2/P4
24 23 22 21 20 19 18 17 16 15 14 13
VDD RX S/N TXCLK RXCLK RXDATA TXDATA TXPSAVE TXENABLE TXOUT BT DOC2 DOC1
C7 C8 C4
VDD
R1
C1
Suggested Clock Circuits XTAL
C3 X1 C2 R2 C9
1
XTAL
R2
1
1 XTAL
XTAL/CLOCK
Crystal Circuit
2
EXT CLK
XTAL/CLOCK
2
EXT CLK
2 XTAL/CLOCK
External Clk > 10.24MHz Circuit
External Clk 10.24MHz Circuit
Figure 3: Recommended External Components Component R1
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Notes 1 2 3 1 4 4
Value 1.0M
Tolerance 5% 10% 10% 10% 10%
Component C4 C5 C6 C7 C8 C9 X1
Notes
Value 0.1F 1.0F
Tolerance 20% 20% 20%
R2 R3 R4 C1 C2 C3
5 6 6 7 8
100pF
Table 2: Recommended External Components Recommended External Component Notes: 1. The RC network formed by R1 and C1 is required between the TX Out pin and the input to the modulator. This network, which can form part of any DC level shifting and gain adjustment circuitry, forms an important part of the transmit signal filtering. The ground connection to the capacitor C1 should be positioned to give maximum attenuation of high-frequency noise into the modulator. The component values should be chosen so that the product of the resistance and the capacitance is:
For a BT of 0.3 For a BT of 0.5
R1C1 = 0.34/bit rate (bps) R1C1 = 0.22/bit rate (bps)
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
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CMX589A PRELIMINARY INFORMATION
Data Rates (kbps) 4 4.8 8 9.6 16 19.2 32 38.4 * 64 * 80 * 128 * 144 * 160 * 176 * 192 *
BT = 0.3 R1 C1 680pF 120k 100k 91k 91k 47k 100k 47k 47k 56k 680pF 470pF 390pF 470pF 180pF 220pF 180pF 100pF
BT = 0.5 R1 C1 470pF 120k 100k 120k 47k 91k 91k 47k 47k 51k 39k 82k 68k 62k 56k 51k 470pF 220pF 470pF 150pF 120pF 150pF 120pF 68pF 68pF 22pF 22pF 22pF 22pF 22pF
* VDD 4.5V, external clock Table 3: Data Rate vs. BT and Selected External Component Values Note: In all cases, the value of R1 should not be less than 20.0k, and that the calculated value of C1 includes calculated parasitic capacitance. 2. R3, R4 and C6 form the gain components for the RX Input signal. R3 should be chosen as required by the signal input level. 3. For bit rate 64kbps, R4 = 100k. For bit rate > 64kbps, R4 = 10k. 4. The values chosen for C2 and C3 (including stray capacitance) should be suitable for the applied VDD and the frequency of X1. As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency. At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less than 2.0K falling to 150 at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins www..com must be minimized. 5. For bit rate 64kbps, C6 = 22pF. For bit rate > 64kbps, C6 = C6 = 41.1pF. 6. C7 and C8 should both be .015F for a data rate of 8kbps, and inversely proportional to the data rate for other data rates, e.g. 0.030F at 4kbps, 1800pF at 64kbps, 680pF at 192kbps. 7. The tolerance of C9 is not very critical because it primarily serves as a DC blocking capacitor. 8. The CMX589A can operate correctly with the Xtal/Clock frequencies between 1.0MHz and 8.2MHz (VDD = 5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V). External clock frequencies up to 25.6MHz (VDD 4.5V) are also supported. (See Table 4 for examples.) For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer. Operation of this device without a Xtal or Clock input may cause device damage. 1 e.g. for 128kbps, 3 bit rate 2 10k
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
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CMX589A PRELIMINARY INFORMATION
4 General Description
4.1 Clock Oscillator Divider
The TX and (nominal) RX data rates are determined by division of the frequency present at the Xtal pin as generated by the on-chip Xtal oscillator, with external components, or supplied from an external source. The division ratio is controlled by the logic level inputs on ClkDivA and ClkDivB pins as shown in Table 4, together with an indication of how various standard data rates may be derived from common P Xtal frequencies.
Data Rate
Xtal/Clk Frequency Division Ratio (ClkDiv A/B)
Inputs ClkDivA ClkDivB 0 0 1 1 * VDD 4.5V 0 1 0 1
Xtal/Clock Frequency (MHz) 24.576* 8.192 4.9152 4.096 2.4576 2.048 12.288/3 12.288/5 6.144/3 Data Rate (kbps) Xtal/Clk Freq Data Rate 128 192* 64* 38.4* 32 19.2 16 256 96* 32 19.2 16 9.6 8 512 48* 16 9.6 8 4.8 4 1024 24* 8 4.8 4
Table 4: Example Clock/Data Rates Note: The device operation is not guaranteed above 200kbps or below 4kbps at the relevant supply voltage.
SETTINGS: D/RATE 4800 bps -BT 0.5 - Rx and Tx Enabled 4.9152MHz XTAL/CLOCK XTAL RxD RxC TxD TxC Rx DATA Rx CLOCK Tx ClOCK Tx DATA PLLacq RxDCacq CMX589A GMSK MODEM Tx Enable ClkDIVA ClkDIVB BT RxHOLD Rx S/N Tx PS Rx PS VDD
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SERIAL I/O PORT
CONTROLLER
Figure 4: Minimum Controller System Connections
4.2
4.2.1
Receive
Rx Signal Path Description
The function of the RX circuitry is to: 1. Set the incoming signal to a usable level. 2. Clean the signal by filtering. 3. Provide DC level thresholds for clock and data extraction. 4. Provide clock timing information for data extraction and external circuits. 5. Provide RX data in a binary form. 6. Assess signal quality and provide Signal-to-Noise information.
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Doc. # 20480183.002
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High Speed GMSK Modem
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CMX589A PRELIMINARY INFORMATION
The output of the radio receiver's Frequency Discriminator should be fed to the CMX589A's RX Filter by a suitable gain and DC level adjusting circuit. This circuit can be built with external components around the onchip RX Input Amplifier. The gain should be set so that the signal level at the RX Feedback pin is nominally 1V peak to peak (for VDD=5.0V) centered around VBIAS when receiving a continuous 1111000011110000.. data pattern. Positive going signal excursions at RX Feedback pin will produce a logic 0 at the RX Data Output. Negative going excursions will produce a logic 1. The received signal is fed through the lowpass RX Filter, which has a -3dB corner frequency of 0.56 times the data bit-rate, before being applied to the Level Measure and Clock and Data extraction blocks. The Level Measuring block consists of two voltage detectors, one of which measures the amplitude of the positive parts of the received signal. The other measures the amplitude of the negative portions. (Positive refers to signal levels higher than VDD/2, and negative to levels lower than VDD/2.) External capacitors are used by these detectors, via the Doc1 & Doc2 pins, to form voltage `hold' or `integrator' circuits. These two levels are then used to establish the optimum DC level decision-thresholds for the Clock and Data extraction, depending upon the RX signal amplitude and any DC offset. 4.2.2 Rx Circuit Control Modes The operating characteristics of the Rx Level Measurement and Clock Extraction circuits are controlled, as shown in Table 6, by logic level inputs applied to the PLLacq, Rx HOLD , and RxDCacq pins to suit a particular application, or to cope with changing reception conditions, reference Figure 5. In general, a data transmission will begin with a preamble, for example, 1100110011001100, to allow the receive modem to establish timing and level-lock as quickly as possible. After the Rx carrier has been detected, and during the time that the preamble is expected, the RxDCacq and PLLacq Inputs should be switched from a logic 0 to a logic 1 so that the Level Measuring and Clock Extraction modes are operated and sequenced as shown. The Rx HOLD input should normally be held at a logic 1 while data is being received, but may be driven to a logic 0 to freeze the Level Measuring Clock Extraction circuits during a fade. If a fade lasts for less than 200 bit periods, normal operation can be resumed by returning the Rx HOLD input to a logic 1 at the end of the fade. For longer fades, it may be better to reset the Level Measuring circuits by placing the RxDCacq to a logic 1 for 10 to 20 bit periods.
Rx HOLD has no effect on the Level Measuring circuits while RxDCacq is at a logic 1, and has no effect on the PLL while PLLacq is at a logic 1.
A logic 0 on Rx HOLD does not disable the Rx Clock output, and the Rx Data Extraction and S/N Detector circuits will continue to operate.
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PREAMBLE Rx Signal Input Rx CARRIER DET (RSSI) Input RxDCacq Rx LEVEL MEASURE MODE PLLacq CLOCK EXTRACTION CCT MODE
DATA
CLAMP
FAST PEAK DETECT
AVERAGING PEAK DETECT 30 BITS
ACQUIRE
MEDIUM BANDWIDTH
NARROW BANDWIDTH
Figure 5: Rx Mode Control Diagram
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CMX589A PRELIMINARY INFORMATION
PLLacq 1
RxHOLD 1 Acquire
PLL Action Sets the PLL bandwidth wide enough to allow a lock to the received signal in less than 8 zero crossings. This mode will operate as long as PLLacq is a logic "1". The correction applied to the extracted clock is limited to a maximum of 1/16th bit-period for every two received zerocrossings. The PLL operates in this mode for a period of about 30 bits immediately following a 1 to 0 transition of the PLLacq input, provided that the Rx HOLD input is a logic 1. The correction applied to the extracted clock is limited to a maximum of 1/64th bit-period for every two received zerocrossings. The PLL operates in this mode whenever the Rx HOLD Input is a logic 1 and PLLacq has been a logic 0 for at least 30 bit periods (after Medium Bandwidth operation for instance). The PLL feedback loop is broken, allowing the RX Clock to freewheel during signal fade periods.
1 to 0
1
Medium Bandwidth
0
1
Narrow Bandwidth
0
0
Hold
Table 5: PLL Action Measurement Operational Modes RxDCacq 0 to 1 RxHOLD X Clamp Rx Level Measure Action Operates for one bit-time after a 0 to 1 transition of the RXDCacq input. The external capacitors are rapidly charged towards a voltage mid-way between the received signal input level and VBIAS, with the charge time-constant being of the order of 0.5 bit-time. The voltage detectors act as peak-detectors, one capacitor is used to capture the positive-going signal peaks of the RX Filter output signal and the other capturing the negativegoing peaks. The detectors operate in this mode whenever the RXDCacq input is at a logic 1, except for the initial 1-bit Clamp-mode time. Provides a slower but more accurate measurement of the signal peak amplitudes. The capacitor charging circuits are disabled so that the outputs of the voltage detectors remain substantially at the last readings (discharging very slowly [time-constant approx. 2,000 bits] towards VBIAS).
1
X
Fast Peak Detect
0 0
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1 0
Averaging Peak Detect Hold
X = Do not care Table 6: Rx Level Measurement Operational Modes 4.2.3 Rx Clock Extraction
Synchronized by a PLL circuit to zero-crossings of the incoming data, the Rx Clock Extraction circuitry controls the Rx Clock output. The Rx Clock is also used internally by the Data Extraction circuitry. The PLL parameters can be varied by the Rx Circuit Control inputs PLLacq and Rx HOLD to operate in one of four PLL modes as described in Table 5 and Table 6. 4.2.4 Rx Data Extraction The RX Data Extraction circuit decides whether each received bit is a 1 or 0 by sampling the received signal, after filtering, and comparing the sample values to an adaptive threshold derived from the Level Measuring circuit. This threshold is adapted from bit to bit to compensate for intersymbol interference caused by the bandlimiting of the overall transmission path and the Gaussian premodulation filter. Extracted data is output from the RX Data pin, and should be sampled externally on the rising edge of the RX CLK.
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CMX589A PRELIMINARY INFORMATION
4.2.5
Rx S/N Detection
The RX S/N Detector system classifies the incoming zero-crossings as GOOD or BAD depending upon the time when each crossing actually occurs with respect to its expected time as determined by the Clock Extraction PLL. This information is then processed to provide a logic level output at the RX S/N pin. A high level indicates a series of GOOD crossings; a low level indicates a BAD crossing. By averaging this output, it is possible to derive a measure of the Signal-to-Noise-Ratio and hence the Bit-Error-Rate of the received signal.
10-1
10-2
10-3 BER 10-4
CMX589A BT = 0.3
10-5
BT = 1.0 (Theoretical) CMX589A BT = 0.5
10-6 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S/N (dB) [Noise Bandwidth = Bit Rate]
Figure 6: Typical Bit-Error-Rate Performance
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Note: Figure 6 indicates typical performance, independent of bit rate (although the applied noise bandwidth is considered to match the bit rate used), radio performance (e.g. IF filter distortion), supply voltage (higher bit rates require VDD 4.5V), and other `real world' factors."
1998 MX-COM, Inc.
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Doc. # 20480183.002
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CMX589A PRELIMINARY INFORMATION
4.2.6
Rx Signal Quality
The effect of input Rx Signal quality on the Rx S/N output is shown in Figure 7.
% High Time 100 90 80 70 60 50 40 30 20 10 0 5 6 7 8 9 S/N (dB) 10 11 12 13
BT = 0.5
BT = 0.3
Figure 7: Typical Rx S/N Output High time (%) vs. Input S/N
4.3
4.3.1
Transmit
TX Signal Path Description
The binary data applied to the TX Data input is retimed within the chip on each rising edge of the TX Clock and then converted to a 1-volt peak-to-peak binary signal centered at VBIAS (for VDD= 5.0V) If the TX Enable input is high, then this internal binary signal will be connected to the input of the lowpass TX Filter, and the output of the filter connected to the TX Out pin. Tx Enable 1 Tx Filter Input Data @ VDD VP-P 5 Tx Out Pin Filtered `Tx Filter Input'
e.g. 1VP-P for VDD=5V
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0
VBIAS
VBIAS via 500k
A `low' input to the TX Enable will connect the input of the TX Filter to VBIAS, and disconnect the TX Out pin from the filter, connecting it instead to VBIAS through a high resistance (nominally 500k). The TX Filter has a lowpass frequency response, which is approximately gaussian in shape as shown in Figure 9, to minimize amplitude and phase distortion of the binary signal while providing sufficient attenuation of the high frequency-components which would otherwise cause interference into adjacent radio channels. The actual filter bandwidth to be used in any particular application will be determined by the overall system requirements. The attenuation-vs.-frequency response of the transmit filtering provided by the CMX589A has been designed to meet the specifications for most GMSK modem systems that are -3dB bandwidth switchable between 0.3 and 0.5 times the data bit-rate (BT). Note: An external RC network is required between the TX Out pin and the input to the Frequency Modulator (see Figure 2 and Figure 3). This network, which can form part of any DC level shifting and gain adjustment circuitry, forms an important part of the transmit signal filtering. The ground connection to capacitor C1 should be positioned to give maximum attenuation of high-frequency noise into the modulator. The signal at Tx Out is centered around VBIAS, going positive for logic 1 (high) level inputs to the Tx Data input and negative for logic 0 (low) inputs. When the transmit circuits are put into a powersave mode (by a logic 1 to the Tx PS pin) the output voltage of the Tx Filter will go to high impedance. When power is subsequently restored to the Tx filter, its output will take several bit-times to settle. The Tx Enable input can be used to prevent these abnormal voltages from appearing at the Tx Out pin.
1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480183.002
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CMX589A PRELIMINARY INFORMATION
1 BIT PERIOD TX DATA SAMPLED BY THE CMX589A AT THESE INSTANCES TX CLK 1.0 s Min. TX Data 1.0 s Min. DON'T CARE DATA MUST BE VALID
TX CLOCK AND RX CLOCK OUTPUTS (MARK/SPACE) DUTY CYCLE NOMINALLY 50%.
RX Data 1.0 s Max. RX CLK EXTERNAL CIRCUITS SHOULD SAMPLE RX DATA AT THIS TIME 1.0 s Max. DATA INVALID DATA VALID
Figure 8: Rx and Tx Clock Data Timings
0
-10 . BT = 0.3 -20 . BT = 0.5
-30 Gain (dB)
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-40
-50
-60
-70 0.01 0.1 Frequency/Bitrate 1 10
Figure 9: Tx Filter Response
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CMX589A PRELIMINARY INFORMATION
BT = 0.3
BT = 0.5
Figure 10: Typical Transmit Eye Patterns
0 -10
BT = 0.3 BT = 0.5
-20
Gain (dB)
-30 -40 -50 -60 -70 0 1.0 Frequency/Bitrate 2.0
Figure 11: Tx Output Spectrum (Random Data)
4.4
Data Formats
The receive section of the CMX589A works best with data which has a reasonably random structure --the data should contain approximately the same number of `ones' as `zeroes' with no long sequences (>100 bits) of consecutive ones or zeroes. Also, long sequences (>100 bits) of 10101010 ... patterns should be avoided.
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For this reason, it is recommended that data be made random in some manner before transmission, for example by exclusive-ORing it with the output of a binary pseudo-random pattern generator. Where data is transmitted in bursts, each burst should be preceded by a preamble designed to allow the receive modem to establish timing and level lock as quickly as possible. This preamble for BT=0.3 should be at least 16 bits long, and should preferably consist of alternating pairs of ones and zeros i.e. 110011001100....; the eye of pattern 10101010 .... has the most gradual slope and will yield poor peak levels for the RX circuits. For BT=0.5 the eye pattern of 10101010... has reduced intersymbol interference and may be used as the preamble (DC Acq pin should be held high during preamble). See Fig. 6.
4.5
Acquisition and Hold Modes
The RXDCacq and PLLacq inputs must be pulsed High for about 16 bits at the start of reception to ensure that the DC measurement and timing extraction circuits lock-on to the received signal correctly. Once lock has been achieved, the above inputs should be taken Low again. In most applications, there will be a DC step in the output voltage from the receiver FM discriminator due to carrier frequency offsets as channels are changed or when the remote transmitter is turned on. The CMX589A can tolerate DC offsets in the received signal of at least 0.5V with respect to VBIAS, (measured at the RX Feedback pin). However, to ensure that the DC offset compensation circuit operates correctly and with minimum delay, the Low to High transition of the RXDCacq and PLLacq inputs should occur after the mean input voltage to the CMX589A has settled to within about 0.1V of its final value. Note: This can place restrictions on the value of any series signal coupling capacitor.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
15
CMX589A PRELIMINARY INFORMATION
As well as using the RX Hold input to freeze the Level Measuring and Clock Extraction circuits during a signal fade, it may also be used in systems which use a continuously transmitting control channel to freeze the RX circuitry during transmission of a data packet, allowing reception to resume afterwards without losing bit synchronization. To achieve this, the CMX589A Xtal clock needs to be accurate enough that the derived RXClock output does not drift by more than about 0.1 bit time from the actual received data-rate during the time that the RXHold input is `Low'. However; the RXDCacq input may need to be pulsed High for 2 bit durations to re-establish the level measurements if the RXHold input is Low for more that a few hundred bit-times (exact number depends on system crystal tolerances). The voltages on the Doc1 and Doc2 pins reflect the average peak positive and negative excursions of the (filtered) receive signal, and could therefore be used to derive a measure of the data signal amplitude. Note: These pins are driven from very high-impedance circuits, so that the DC load presented by any external circuitry should exceed 10M to VBIAS.
5 Application
5.1 Radio Channel Requirements
To achieve legal adjacent channel performance at high bit-rates, a radio with an accurate carrier frequency and an accurate modulation index is required. For optimum channel utilization, (e.g. low BER and high datarates) attention must be paid to the phase and frequency response of both the IF and baseband circuitry. 5.1.1 Bit Rate, BT, and Bandwidth Channel spacing Allowable adjacent channel interference TX filter bandwidth Peak carrier deviation (Modulation Index) TX and RX carrier frequency accuracies Modulator and Demodulator linearity RX IF filter frequency and phase characteristics Use of error correction techniques Acceptable error-rate As a guide to MOBITEX operation, a raw data-rate of 8kbps at 12.5kHz channel spacing may be achievable depending on local regulatory requirements- using a 2kHz maximum deviation, a BT of 0.3, and no more than 1.5kHz discrepancy between Tx & Rx carrier frequencies. Forward error correction (FEC) could then be used with interleaving to reduce the effect of burst errors.
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The maximum data rate that can be transmitted over a radio channel depends on the following:
Reducing the data-rate to 4.8kbps would allow the BT to be increased to 0.5, improving the error-rate performance. 5.1.2 FM Modulator, Demodulator and IF For optimum performance, the eye pattern of the received signal (when receiving random data) applied to the CMX589A should be as close as possible to the Transmit eye pattern examples shown in Figure 10. Of particular importance are general symmetry, cleanliness of the zero-crossings, and for a BT of 0.3, the relative amplitude of the inner eye opening. To achieve this, attention must be paid to: Linearity and frequency/phase response of the Tx frequency modulator. Unless the transmit data is especially encoded to remove low frequency components, the modulator frequency response should extend down to a few hertz. This is because two-point modulation is necessary for synthesized radios. Bandwidth & phase response of the RX IF filters. Accuracy of the Tx and Rx carrier frequencies -any difference will shift the received signal towards one of the skirts of the IF filter response.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
16
CMX589A PRELIMINARY INFORMATION
Ideally, the Rx demodulator should be DC coupled to the CMX589A RX Signal In pin (with a DC bias added to center the signal at the RX Feedback pin at VDD/2 [VBIAS]). However, AC coupling can be used provided that: The 3dB cut-off frequency is 20Hz or below (i.e. a 0.1F capacitor in series with 100k). The data does not contain long sequences of consecutive ones or zeroes. Sufficient time is allowed after a step change at the discriminator output (resulting from channel changing or the appearance of a RF carrier) for the voltage into the CMX589A to settle before the RXDCacq line is strobed. 5.1.3 Two-Point Modulation When designing the CMX589A into a radio that uses a frequency synthesizer, a two-point modulation technique is recommended. This is both to prevent the radio's PLL circuitry from counteracting the modulation process, and to provide a clean flat modulation response down to DC. Figure 12 shows a suggested basic configuration to provide a two-point modulation drive from the CMX589A TX Output using MX-COM's MX019 Digitally Controlled Quad Amplifier Array. The MX019 elements provide individual set-up, calibration and dynamic control of modulation levels. Level setting control of the amplifiers/attenuators of the MX019 is via an 8-bit data word. Note that the MX019 frequency response supports data rates as high as 8kbps. With reference to Figure 12: The buffer amplifier is required to prevent loading of the CMX589A external RC circuit. Stage B, with R1/R2, provides suitable signal and DC levels for the VCO varactor; C1 is RF decoupling. The drive level should be adjusted (digitally) to provide the desired deviation. Stage C, with R3/R4, provides the Reference Oscillator drive (application dependent). This parameter is set by adjusting for minimum AC signal on the PLL control voltage with a low-frequency modulating signal (inside the PLL bandwidth) applied. Stage D could be used with the components shown if a negative reference drive is required. Stage A provides buffering and overall level control.
CONTROL +3dB to -3dB B TX OUT VSS
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TX VCO
+14dB to -14dB
Buffer
R1 R2
VVCO C1
CMX589A
A
External RC See Fig.3 C
+3dB to -3dB R3
To TX REF Osc (+)
VREF(+)
With reference to the MX019 Data Sheet Stage A = MX019 Channel 4 Stage B = MX019 Channel 1 Stage C = MX019 Channel 2 Stage D = MX019 Channel 3 Note: 1. All stages of the MX019 are 'inverting' stages. 2. Components R1-R6 should produce the proper output signal levels for interface into the modulator.
R4 +3dB to -3dB D R5 R6 VREF(-) To TX REF Osc (-)
Figure 12: An Example of Two-Point Modulation Drive with Individual Adjustment Using the MX019
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
17
CMX589A PRELIMINARY INFORMATION
5.2
AC Coupling of Tx and Rx Signals
In practical applications, it is possible to arrange AC coupling between the CMX589A Tx Output and the frequency modulator to cut-off at a very low frequency, such as 5.0Hz. AC coupling between the receive discriminator and the input of the CMX589A may need a shorter time-constant to avoid problems from voltage steps at the output of the discriminator when changing channels or when the distant transmitter turns on. For these reasons, as well as to maintain reasonable BER, the optimum -3dB cut-off frequencies are around 5.0Hz in the Tx path and 20.0Hz in the Rx path. Figure 13 shows the typical static Bit-Error-Rate performance of the CMX589A operating under nominal conditions for various degrees of AC coupling at the Rx input and the Tx output. Data Rate = 8kbps
10-1
VDD = 5.0V
TAMB = 25C
Tx BT = 0.3
10-2
BER
10-3 TX and RX DC coupled TX 5Hz, RX DC coupled 10-4 TX 5Hz, RX 10Hz TX 5Hz, RX 30Hz TX 5Hz, RX 100Hz 10-5 4 5 6 7 8 9 10 11 12 13
S/N (dB) (noise in 8kHz bandwidth)
Figure 13: Effect of AC Coupling on Typical Bit-Error Rate
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at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 14, the time for this step to decay to 37% of its original value is `RC' where: RC
1 2(the 3dB cutoff frequency of the RC network)
which is 32ms, or 256 bit times at 8kbps, for a 5Hz network.
Figure 14: Decay time-AC Coupling
1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
18
CMX589A PRELIMINARY INFORMATION
6 Performance Specifications
6.1
6.1.1
Electrical Specifications
Absolute Maximum Limits
Exceeding these maximum ratings can result in damage to the device. General Supply (VDD-VSS) Voltage on any pin to VSS Current VDD VSS Any other pin D2 / P4 Packages Total allowable Power dissipation at TAMB = 25C Derating above 25C Operating Temperature Storage Temperature D5 / E2 Packages Total allowable Power dissipation at TAMB = 25C Derating above 25C Operating Temperature Storage Temperature -40 -55 9 85 125 -40 -55 Notes Min. -0.3 -0.3 -30 -30 -20 Typ. Max. 7.0 VDD + 0.3 30 30 20 800 13 85 125 550 Units V V mA mA mA mW mW/C above 25C C C mW mW/C above 25C C C
Table 7: Absolute Maximum Ratings 6.1.2 Operating Limits
Correct Operation of the device outside these limits is not implied.
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Notes Supply (VDD-VSS) Operating Temperature Rx and Tx Data Rate VDD 3.0V VDD 4.5V Xtal Frequency VDD 3.0V VDD 4.5V High Pulse Width Low Pulse Width 1 1
Min. 3.0 -40 4 4 1.0 1.0 15 15
Typ. 3.3/5.0
Max. 5.5 85 32 200 5.0 25.6
Units V C kbps kbps MHz MHz ns ns
Table 8: Operating Limits Operating Limits Notes 1. Timing for an external clock input to the Xtal/Clock pin.
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
19
CMX589A PRELIMINARY INFORMATION
6.1.3
Operating Characteristics
For the following conditions unless otherwise specified. VDD = 5.0V @ TAMB = 25C Xtal/Clock Frequency = 4.096MHz, Data Rate = 8kbps, Noise Bandwidth = Bit Rate Static Values Supply Current IDD (VDD = 3.0V) Notes 1 Min. Typ. Max. Units
Tx PS 1 0 1 0
Rx PS 1 1 0 0 1 1 0 0
0.5 1.0 1.0 1.5 1.0 2.0 3.0 4.0 3.5 2 -5.0 4.6 0.4 -85 85 1.5 5.0
mA mA mA mA mA mA mA mA V V A V V mV
IDD (VDD = 5.0V) 1 0 1 0 Input Logic Level Logic 1 Input Level Logic 0 Input Level Logic Input Current Output Logic Level Logic 1 Output Level (IOH = 120A) Logic 0 Output Level (IOL = -120A) Transmit Parameters Tx OUT pin DC bias shift caused by change from Tx Enable = 0 to Tx Enable = 1 while Tx PSAVE = 0 at 25C Tx OUT, Output Impedance Tx Out, Level
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3 4, 10 12 5 5 6 0.8 -0.125
1.0 1.0 1.2 0.125 2.0 1.5 4.0 2.5 2.0
k VP-P V bitperiods bitperiods bitperiods
Output DC Offset Tx Data Delay BT = 0.3 BT = 0.5 Tx PS to Output-Stable time
Receive Parameters Rx Amplifier Input Impedance Output Impedance Voltage Gain Rx Filter Signal Input Level Rx Time Delay 7 8, 10 9
1.0 10.0 0.7 50.0 1.0 1.3 3.0
M K dB VP-P bitperiods
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
20
CMX589A PRELIMINARY INFORMATION
Static Values On-Chip Xtal Oscillator RIN ROUT Voltage Gain
Notes
Min. 10.0
Typ.
Max.
Units M
11 11 Table 9: Operating Characteristics
50.0 25.0
k dB
Operating Characteristics Notes: 1. Not including current drawn from the CMX589A pins by external circuitry. See Absolute Maximum Ratings. 2. For VIN in the range VSS to VDD. 3. For a load of 10K or greater. Tx PS input at logic 0; Tx Enable = 1. 4. Data pattern of 1111000011110000... 5. Measured between the rising edge of Tx Clock and the center of the corresponding bit at Tx Out. 6. Time between the falling edge of the Tx PS and the Tx Out voltage stabilizing to normal output levels. 7. For a load of 10k or greater. Rx PS input at logic 0. 8. For optimum performance, Measured at the Rx Feedback pin for an 1111000011110000... pattern. 9. Measured between the center of bit at Rx Signal In and corresponding rising edge of the Rx Clock. 10. Levels are proportional to applied VDD 11. Small signal measurement at 1.0kHz with no load on Xtal output. 12. (Tx OUT enabled DC level) - (Tx Out disabled DC level) when transmitting a repeating 11110000 bit pattern.
6.2
Packages
A
A B C E H J L P T Y
Package Tolerances
DIM. MIN. TYP. MAX.
ALTERNATIVE PIN LOCATION MARKING www..com
B
E L
PIN 1 Y C H J P
T
0.311 (7.90) 0.303 (7.70) 0.169 (4.30) 0.177 (4.50) ---------0.047 (1.20) 0.248 (6.30) 0.256 (6.50) 0.002 (0.05) 0.006 (0.15) 0.007 (0.17) 0.012 (0.30) 0.020 (0.50) 0.030 (0.75) 0.0256 (0.65) 0.003 (0.08) 0.008 (0.20) 0 8
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 15: 24-pin TSSOP Mechanical Outline: Order as part no. CMX589AE2
1998 MX-COM, Inc.
www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
High Speed GMSK Modem
21
CMX589A PRELIMINARY INFORMATION
A
Package Tolerances
Z B E L
DIM. A B C E H J L P T X Y Z MIN. TYP. MAX.
0.318 (8.07) 0.328 (8.33) 0.205 (5.20) 0.213 (5.39) 0.066 (1.67) 0.079 (2.00) 0.301 (7.65) 0.312 (7.90) 0.002 (0.05) 0.008 (0.21) 0.010 (0.25) 0.015 (0.38) 0.022 (0.55) 0.037 (0.95) 0.026 (0.65) 0.005 (0.13) 0.009 (0.22) 0 8 7 9 10 4
PIN 1 X Y H J P
T
C
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 16: 24-pin SSOP Mechanical Outline: Order as part no. CMX589AD5
Package Tolerances
A Z B E W L PIN 1 X Y CK H J P T
DIM. A B C E H J K L P T W X Y Z MIN.
0.597 (15.16) 0.286 (7.26) 0.093 (2.36) 0.390 (9.90) 0.003 (0.08) 0.013 (0.33) 0.036 (0.91)
TYP.
MAX.
0.613 (15.57) 0.299 (7.59) 0.105 (2.67) 0.419 (10.64) 0.020 (0.51) 0.020 (0.51) 0.046 (1.17)
ALTERNATIVE PIN LOCATION MARKING
0.050 (1.27) 0.016 (0.41) 0.050 (1.27) 0.009 (0.23) 45 0 5 5 10 7 0.0125 (0.32)
NOTE : All dimensions in inches (mm.) Angles are in degrees
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Figure 17: 24-pin SOIC Mechanical Outline: Order as part no. CMX589AD2
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP. MAX.
1.270 (32.26) 1.200 (30.48) 0.555 (14.04) 0.500 (12.70) 0.151 (3.84) 0.220 (5.59) 0.600 (15.24) 0.670 (17.02) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 0.121 (3.07) 0.160 (4.05) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7 NOTE : All dimensions in inches (mm.) Angles are in degrees
B
E1
Y
E
PIN1
T
K H L J J1 P
C
Figure 18: 24-pin PDIP Mechanical Outline: Order as part no. CMX589AP4
1998 MX-COM, Inc. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480183.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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